Four quadrant multiplier using pulse width modulators and the digital exclusive-or

ABSTRACT

There is disclosed a four quadrant multiplier circuit and method in which the signals to be multiplied are used to pulse width modulate carrier signals of different frequencies, respectively, and the resulting pulse width modulated signals are applied to an exclusive - OR circuit. The output of the exclusive - OR circuit is filtered to remove the carrier signals and any beat frequency between the carriers so that the output will be proportional to the bi-polar product of the signals being multiplied.

United States Patent Grobert 51 May 30, 1972 [72] Inventor: Paul H. Grobert, Nutley, NJ.

[73] Assignee: Communications & Systems, Inc.

[22] Filed: July 23, 1970 [21] Appl. No.1 57,478

[52] U.S. Cl ..235/194, 307/229, 328/160 [51] Int. Cl. ..G06g 7/16 [58] Field ofSearch ..235/194, 195, 196, 150.52; 207/229, 230, 295, 216; 328/160, 161; 331/38 [56] References Cited UNITED STATES PATENTS 3,521,038 7/1970 Gilbert ..235/194 X CONDITION e MODULATOR OUTPUT egMODULATOR OUTPUT WITH eg O EXCLUSIVE-OR OUTPUT NOTE SYMMETRICAL OUTPUT Meyer ..235/194 3,092,720 6/1963 De Vriver et al. ...235/l94 X 3,525,861 4/1970 Alexander ...235/l94 X 3 ,466,460 9/ l 969 Connolly ..235/194 X Primary Examiner-Joseph F. Ruggiero Attorney-Beveridge & De Grandi [57] ABSTRACT There is disclosed a four quadrant multiplier circuit and method in which the signals to be multiplied are used to pulse width modulate cam'er signals of different frequencies, respectively, and the resulting pulse width modulated signals are applied to an exclusive OR circuit. The output of the exclusive OR circuit is filtered to remove the carrier signals and any beat frequency between the carriers so that the output will be proportional to the bi-polar product of the signals being multiplied.

2 Claims, 4 Drawing figures ZERO AVERAGE VALUE ZERO AVERAGE VALUE EXCLUSIVE-0R OUTPUT -v POSITIVE AVERAGE VALUE Patented Ma, 30, 1972 3,666,933.

2 Shoets-$heet 1 FM (ARBITRARY) l0 PULSE /PULSE WIDTH PR rm A MOTH m 0P0 0N LTOe MOD. 12

1 I4A l4 e FILTER l5 l6 Avlvlv K I3 I l I48 FICL'PRIORART yr 2 INVERTING AMPLIFIER 22 l PULSE e WIDTH MOD.

- EXCLUSIVE-0R 24) fi T l z PULSE wmm MOD.

- INVENTOR HQ 2 FB PAUL HENRY GROBERT BY (5 12 ir;

ATTORNEYS Patented May 30, 1972 e O EXCLUSIVE-0R OUTPUT EXCLUSIVE-OR OUTPUT FIG. 3

C NDlTION 61 PO ITIVE e POSITWE EXCLUSIVE-OR OUTPUT e; NEGATIVE e2 POSITIVE EXCLUSIVE-OR OUTPUT e POSITIVE e NEGATIVE EXCLUSIVE OR OUTPUT e NEGATIVE e2 NEGATIVE EXCLUSIVE-OR OUTPUT 2 Sheets-Sheet 2 q MODULATOR OUTPUW +V I ,W L

NOTE SYMMETRICAL OUTPUT ZERO AVERAGE VALUE \ZERO AVERAGE VALUE w JLJTJ J H A n n W C POSITIVE AVERAGE VALUE J l L llllllllllllllllll lllllllllllllw -MLLHIIIIIIlI-IIITIIITLLLUJJT PosmvE AVERAGE I L T lllll|||||||Lllllllllllllllllli *Y TITTITTTTTITTTTTTFTTTTFTT 1 NEGATTvE AVERAGE l I L THU\IlllllIIIIIIIIIIIIIIIIIIT llllllilllllllllllllll l I \NEGATIVE AVERAGE I I T Tlllilllllllll!IIIIITIIIIIITHILIV IIIITIIIIIHHIIW PosTTTvE AVERAGE FOUR QUADRANT MULTIPLIER USING PULSE WIDTH MODULATORS AND THE DIGITAL EXCLUSIVE-OR The invention hereindescribed was made in the course of or under a contract or subcontract thereunder, or grant, with the Department of the Air Force.

The present invention is directed to a signal processing system and circuit for performing four quadrant multiplication, and, more particularly to a circuit and method for obtaining the bi-polar product of two signed signal voltages where the signal voltages are first converted to pulse width modulations of a pair of carriers and in which the multiplication of the two signals is achieved in an exclusive OR gate element.

BACKGROUND OF THE INVENTION In signal processing systems, the need often arises to obtain the bi-polar product of two signed signal voltages (e.g., four quadrant multiplication). This has been done in a number of ways in the past and a standard prior art circuit for performing this function is shown in FIG. 1 of the drawing where one input signal voltage e,, as applied to input terminal 10, is used to pulse width modulate a carrier frequency F (which is of an arbitrarily selected frequency) so that the output of the pulse width modulator is a digital pulse frequency train wherein the pulse width is proportional to e,. The second signal voltage e is passed through an inverting amplifier 13 so that there is presented to contacts or terminals 14A and 14B of analog switch 14 the signal voltage e and the inverse thereof, respectively. The output of pulse width modulator 14 has a duty cycle which is a linear function of e (50 percent when e equals zero) and, as indicated above, is at some arbitrarily selected frequency or pulse rate F The output of pulse width modulator 12 is used to operate analog switch 14, switching it between terminal 14A (signal voltage e and terminal 14B (the inverse of signal voltage 1? e.g. e The voltage output from switch 14 is then filtered in a filter 15 which filters out the pulse width modulation frequency P so that the output signal voltage appearing on terminal 16 is the bi-polar product of the two signed voltages.

In accordance with the present invention, two pulse width modulators are utilized with a digital exclusive-OR gate circuit replacing the above-described analog switch.

In the accompanying drawing,

FIG. 1 described above illustrates, for comparison purposes, a prior art multiplier circuit,

FIG. 2 is a circuit diagram of a multiplier circuit incorporating the invention and FIGS. 3 (A, B and C) and FIGS. 4 (I, II, III and IV) are waveform diagrams which are included to illustrate operation of the circuit shown in FIG. 2.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to FIG. 2 which is a preferred embodiment of a four quadrant multiplier circuit incorporating the invention, there is disclosed a circuit for obtaining the bi-polar product of two signed signal voltages e and e applied to input terminals 20 and 21, respectively. Signed signal voltage e is applied to a linear pulse width modulator 22 which has applied thereto a carrier frequency F which is at an arbitrarily selected frequency or pulse rate. The output of pulse width modulator 22, for various possible combinations of conditions of input signal voltage e, relative to e are illustrated at the top line of each of FIGS. 3A, 38, FIG. 3C and FIGS. 41, 4Il, 4111, and 41V. I

Similarly, signed input signal voltage e is applied to input terminal 21 and hence to linear pulse width modulator 23. An important and necessary feature of the invention is that the carrier frequency or pulse rate P applied to pulse width modulator 23 must be different than the frequency or pulse rate F applied to pulse width modulator 22. This difference in frequency will appear as a beat frequency in the output and must be filtered out along with two modulator frequencies F and P in output filter 25. The pulse width modulator 23 signal, the pulse widths of which are proportional to signed signal voltage e are shown at the center line in FIGS. 3A, 3B and 3C as well as the center line in FIGS. 41, 411, 4111, 4IV, for the various combinations of possible conditions of input signal voltage e relative to e,.

These two output signals, being of digital form and having 'pulse widths which are proportional to the respective input signed signal voltages, are applied to a digital exclusive OR gate 24. characteristically, exclusive OR gate circuit 24 has an output or value of one when either of the pulse width modulated signal voltages applied thereto has a value of one but no output when both have a like value. This property of the exclusive OR circuit which allows bi-polar multiplication is graphically illustrated in FIGS. 3A, 3B and 3C. Referring to FIG. 3A, with the condition being that both signal voltages e and e are equal to zero, the corresponding modulator output (from pulse width modulators 22 and 23 respectively) has a 50 percent duty cycle. Thus, the exclusive 0R circuit 24 has an output which is symmetrical and the average value of the output from low pass filter 25 is zero. If signal voltage e, is not zero, the output of modulator 22 has other than a 50 percent duty cycle. Thus, the duty cycle of the pulse trains vaties in amount and direction from 50 percent according to the amplitude and polarity, respectively, of the corresponding signal voltage to be multiplied. With reference to FIG. 38, with signal voltage e being equal to zero, the average exclusive OR circuit output is again zero. The same is true for when signed signal voltage e, is equal to zero and signed signal voltage e is not zero. Thus, if both e and e, are other than zero, the magnitude of the average exclusive OR output will be proportional to e 2 (see FIG. 3C).v

FIGS. 4I, 4H, 4H] and 4 IV demonstrate the four combinations of polarity conditions of input signals e and e, and resulting output from exclusive OR circuit 24. When signal e and e have the same polarity, (e.g. both are positive or both are negative) the output from exclusive OR circuit 24 will have a positive average value as illustrated in FIGS. 4] and 41V. When signals e, and e have differentpolarities, (e.g. one positive and one negative) the output from exclusive OR circuit 24 will have a negative average value as illustrated in FIGS. 4" and 4III.

It will be understood that the above-described embodiment of the invention is illustrative only and modifications thereof will occur to those skilled in the art. Hence, the invention is not to be limited to the specific circuit and method disclosed herein.

In the claims:

1. A multiplier circuit for obtaining the bi-polar product of at least a pair of signed signal voltages, comprising,

a plurality of pulse width modulator means, one for each signed signal voltage, and each pulse width modulator having a different operating frequency and a duty cycle of approximately 50 percent when the input signal voltage applied thereto is zero, and each producing a train of pulses in which the pulse widths thereof, respectively, are proportional to one of said signed signal voltages applied to a pulse width modulator,

a digital exclusive-OR logic gate circuit having a plurality of inputs corresponding to the number of pulse width modulated pulse trains, and

means for deriving an output from said digital logic gate element which is the bi-polar product of said signal voltages including a filter for removing said modulator operating frequencies and any beat frequencies therebetween.

2. A method of obtaining the bi-polar product of at least a pair of signed signal voltages, comprising,

for each signal to be multiplied, producing a digital pulse train at a selected frequency, different for each train, and in which the width of the pulses in a train is proportional to one of the signed signal voltages, whereby when one of said signal voltages is zero the digital pulse train produced thereby is approximately 50 percent and when a signal voltage is other than zero the duty cycle varies in amount and direction according to the amplitude and polarity of the corresponding signal voltage, and applying the digital pulse trains so produced to a digital logic gate element whereby there will be an output only when either said signals are other than zero and at times 5 when only one pulse in any pulse train is present. 

1. A multiplier circuit for obtaining the bi-polar product of at least a pair of signed signal voltages, comprising, a plurality of pulse width modulator means, one for each signed signal voltage, and each pulse width modulator having a different operating frequency and a duty cycle of approximately 50 percent when the input signal voltage applied thereto is zero, and each producing a train of pulses in which the pulse widths thereof, respectively, are proportional to one of said signed signal voltages applied to a pulse width modulator, a digital exclusive-OR logic gate circuit having a plurality of inputs corresponding to the number of pulse width modulated pulse trains, and means for deriving an output from said digital logic gate element which is the bi-polar product of said signal voltages including a filter for removing said modulator operating frequencies and any beat frequencies therebetween.
 2. A method of obtaining the bi-polar product of at least a pair of signed signal voltages, comprising, for each signal to be multiplied, producing a digital pulse train at a selected frequency, different for each train, and in which the width of the pulses in a train is proportional to one of the signed signal voltages, whereby when one of said signal voltages is zero the digital pulse train produced thereby is approximately 50 percent and when a signal voltage is other than zero the duty cycle varies in amount and direction according to the amplitude and polarity of the corresponding signal voltage, and applying the digital pulse trains so produced to a digital logic gate element whereby there will be an output only when either said signals are other than zero and at times when only one pulse in any pulse train is present. 